Various microelectronic, optoelectronic, and microfabrication applications require thin layers of crystalline materials as a starting structure for fabricating various useful systems. Traditional methods for cutting thin layers (e.g., wafers) from large diameter crystalline ingots of crystalline materials have involved use of wire saws. Wire sawing technology has been applied to various crystalline materials, such as silicon, sapphire, and silicon carbide. A wire saw tool includes an ultra-fine steel wire (typically having a diameter of 0.2 mm or less) that is passed through grooves of one or many guide rollers. Two slicing methods exist, namely, loose abrasive slicing and fixed abrasive slicing. Loose abrasive slicing involves application of a slurry (typically a suspension of abrasives in oil) to a steel wire running at high speed, whereby the rolling motion of abrasives between the wire and the workpiece results in cutting of an ingot. Unfortunately, the environmental impact of slurry is considerable. To reduce such impact, a wire fixed with diamond abrasives may be used in a fixed abrasive slicing method that requires only a water-soluble coolant liquid (not a slurry). High-efficiency parallel slicing permits a large number of wafers to be produced in a single slicing procedure. FIG. 1 illustrates a conventional wire saw tool 1 including parallel wire sections 3 extending between rollers 4A-4C and arranged to simultaneously saw an ingot 2 into multiple thin sections (e.g., wafers 8A-8G) each having a face generally parallel to an end face 6 of the ingot 2. During the sawing process, the wire sections 3 supported by the rollers 4A-4C may be pressed in a downward direction 5 toward a holder 7 underlying the ingot 2. If the end face 6 is parallel to a crystallographic c-plane of the ingot 2, and the wire sections 3 saw through the ingot 2 parallel to the end face 6, then each resulting wafer 8A-8G will have an “on-axis” end face 6′ that is parallel to the crystallographic c-plane.
It is also possible to produce vicinal (also known as offcut or “off-axis”) wafers having end faces that are not parallel to the crystallographic c-plane. Vicinal wafers (e.g., of SiC) having a 4 degree offcut are frequently employed as growth substrates for high-quality physical vapor transport and epitaxial growth of other materials (e.g., AlN and other Group III nitrides). Vicinal wafers may be produced either by growing an ingot in a direction away from the c-axis (e.g., growing over a vicinal seed material) and sawing the ingot perpendicular to the ingot sidewalls), or by growing an ingot starting with an on-axis seed material and sawing the ingot at an angle to that departs from perpendicular to the ingot sidewalls.
Wire sawing of semiconductor materials involves various limitations. Kerf losses based on the width of material removed per cut are inherent to saw cutting, and represent a significant loss of semiconductor material. Wire saw cutting applies moderately high stress to wafers, resulting in non-zero bow and warp characteristics. Processing times for a single boule (or ingot) are very long, and events like wire breaks can increase processing times and lead to undesirable loss of material. Wafer strength may be reduced by chipping and cracking on the cut surface of a wafer. At the end of a wire sawing process, the resulting wafers must be cleaned of debris.
In the case of silicon carbide (SiC) having high wear resistance (and a hardness comparable to diamond and boron nitride), wire sawing may require significant time and resources, thereby entailing significant production costs. SiC substrates enable fabrication of desirable power electronic, radio frequency, and optoelectronic devices. SiC occurs in many different crystal structures called polytypes, with certain polytypes (e.g., 4H—SiC and 6H—SIC) having a hexagonal crystal structure.
FIG. 2 is a first perspective view crystal plane diagram showing the coordinate system for a hexagonal crystal such as 4H—SiC, in which the c-plane ((0001) plane, corresponding to a [0001] (vertical) direction of crystal growth) is perpendicular to both the m-plane ((1100) plane) and the a-plane ((1120) plane), with the (1100) plane being perpendicular to the [1100] direction, and the (1120) plane being perpendicular to the [11{umlaut over (2)}0] direction. FIG. 3 is a second perspective view crystal plane diagram for a hexagonal crystal, illustrating a vicinal plane 9 that is non-parallel to the c-plane, wherein a vector 10 (which is normal to the vicinal plane 9) is tilted away from the [0001] direction by a tilt angle β, with the tilt angle β being inclined (slightly) toward the [1120] direction. FIG. 4A is a perspective view wafer orientation diagram showing orientation of a vicinal wafer 11A relative to the c-plane ((0001) plane), in which a vector 10A (which is normal to the wafer face 9A) is tilted away from the [0001] direction by a tilt angle β. This tilt angle β is equal to an orthogonal tilt (or misorientation angle) β that spans between the (0001) plane and a projection 12A of the wafer face 9A. FIG. 4B is a simplified cross-sectional view of the vicinal wafer 11A superimposed over a portion of an ingot 14A (e.g., an on-axis ingot having an end face 6A parallel to the (0001) plane) from which the vicinal wafer 11A was defined. FIG. 4B shows that the wafer face 9A of the vicinal wafer 11A is misaligned relative to the (0001) plane by a tilt angle β.
FIG. 5 is a top plan view of an exemplary SiC wafer 25 including an upper face 26 (e.g., that is parallel to the (0001) plane (c-plane), and perpendicular to the direction) and laterally bounded by a generally round edge 27 (having a diameter D) including a primary flat 28 (having a length LF) that is perpendicular to the (1120) plane, and parallel to the [1120] direction. A SiC wafer may include an outer surface that is misaligned with (e.g., off-axis at an oblique angle relative to) the c-plane.
Due to difficulties associated with making and processing SiC, SiC device wafers have a high cost relative to wafers of various other semiconductor materials. Typical kerf losses obtained from wire sawing SiC may be approximately 250 microns or more per wafer, which is quite significant considering that the wafers resulting from a wire sawing process may be roughly 350 microns thick and subsequently thinned (by grinding) to a final thickness of approximately 100 to 180 microns depending on the end use. It has been impractical to slice wafers thinner than about 350 microns considering wire sawing and device fabrication issues.
To seek to address limitations associated with wire sawing, alternative techniques for removing thin layers of semiconductor materials from bulk crystals have been developed. One technique involving removal of a layer of silicon carbide from a larger crystal is described in Kim et al., “4H—SiC wafer slicing by using femtosecond laser double pulses,” Optical Materials Express 2450, vol. 7, no. 7 (2017). Such technique involves formation of laser-written tracks by impingement of laser pulses on silicon carbide to induce subsurface damage, followed by adhesion of the crystal to a locking jig and application of tensile force to effectuate fracture along a subsurface damage zone. Use of the laser to weaken specific areas in the material followed by fracture between those areas reduces the laser scanning time.
Additional separation techniques involving formation of laser subsurface damage with a pulsed laser beam to a SiC ingot and subsequent inducement of fracture by application of ultrasonic vibration are disclosed by U.S. Pat. Nos. 9,925,619 and 10,155,323 to Disco Corporation. Additional techniques for removing thin layers of semiconductor materials from bulk crystals are disclosed in U.S. Patent Application Publication No. 2018/0126484A1 to Siltectra GmbH.
Tools for forming laser subsurface damage in semiconductor materials are known in the art and commercially available from various providers, such as Disco Corporation (Tokyo, Japan). Such tools permit laser emissions to be focused within an interior of a crystalline substrate, and enable lateral movement of a laser relative to the substrate. Typical laser damage patterns include formation of parallel lines that are laterally spaced relative to one another at a depth within a crystalline material substrate. Parameters such as focusing depth, laser power, translation speed, etc. may be adjusted to impart laser damage, but adjustment of certain factors involves tradeoffs. Increasing laser power tends to impart greater subsurface damage that may increase ease of fracturing (e.g., by reducing the stress required to complete fracturing), but greater subsurface damage increases surface irregularities along surfaces exposed by fracturing, such that additional processing may be required to render such surfaces sufficiently smooth for subsequent processing (e.g., for incorporation in electronic devices). Reducing lateral spacing between subsurface laser damage lines may also increase ease of fracturing, but a reduction in spacing between laser damage lines increases the number of translational passes between a substrate and a laser, thereby reducing tool throughput. Additionally, results obtained by laser processing may vary within a substrate, depending on lateral or radial position at a particular vertical depth, and/or depending on vertical position of a substrate face relative to its original growth position as part of an ingot.
Variations in material and/or optical properties within a thick substrate such as a SiC ingot, and also among different ingots of the same composition, render it challenging to easily fabricate wafers of repeatably uniform thickness by laser processing and subsequent fracture while avoiding unnecessary material loss.
Accordingly, the art continues to seek improved laser-assisted methods for parting or removing relatively thin layers of crystalline (e.g., semiconductor) material from a substrate to address issues associated with conventional methods.